The present invention relates to a semiconductor device and a method for fabricating the same, more specifically to a semiconductor device including contact holes which are micronized suitably to be used in a highly integrated DRAM and a method for fabricating the same.
As semiconductor devices are larger-scaled and higher-integrated, it is essential to micronize contact holes for interconnecting metallization layers. To this end various structures of semiconductor devices, which permit micronized contact holes to be formed, and various methods for fabricating semiconductor devices of the structures have been proposed.
Conventional semiconductor device fabricating methods which permit micronized contact holes to be formed will be explained with reference to FIGS. 47A-47C, 48A-48B, 49A-49C, 50A-50B, 51A-51D and 52A-52B. FIGS. 47A-47C and 48A-48B are views explaining a first conventional method. FIGS. 49A-49C and 50A-50B are views explaining a second conventional method. FIGS. 51A-51D and 52A-52B are views explaining a third conventional method.
In the first conventional method, two gate electrodes 204 are formed adjacent to each other on a silicon substrate 200 through a gate insulation film 202.
Then, ions are implanted into the silicon substrate 200 with the gate electrodes 204 as a mask to form an impurity diffused layer 206 in the silicon substrate 200 on both sides of the gate electrodes 204.
Then, a silicon oxide film is deposited on the entire surface by, e.g., CVD (Chemical Vapor Deposition) method, and the surface of the silicon oxide film is planarized to form an inter-layer insulation film 208 of the silicon oxide film (FIG. 47A).
A contact hole which reaches the impurity diffused layer 206 formed in the silicon substrate 200 between the gate electrodes 204 is formed in the inter-layer insulation film 208. First, the contact hole 210 is opened between the gate electrodes 204 by the usual lithography (FIG. 47B), and then a silicon oxide film is grown on the entire surface, and a sidewall insulation film 212 of the contact hole 210 is formed by anisotropic etching which vertically advances (FIG. 47C).
In the first conventional method the contact hole 210 which thus arrives at the impurity diffused layer 206 is formed, whereby the contact hole 210 can have a size of below a resolution size limit.
The state shown in FIG. 47C is based on the assumption that no disalignment takes place in the lithography step.
However, in the first conventional method when disalignment takes place in the lithography step for forming the contact hole, the gate electrode 204 is often exposed in the contact hole 210 as shown in FIG. 48A. In this case, the disalignment is small, the gate electrodes 204 are completely covered with the sidewall insulation film 212, but when the disalignment is large as shown in FIG. 48B, a surface of the gate electrode 204 is exposed in the contact hole 210, and a metallization layer (not shown) formed in the contact hole 210 short-circuits with the gate electrode 204.
In view of this, in the second conventional method, as shown in FIGS. 49A-49C, an etching stopper film 214 having etching characteristics different from those of the inter-layer insulation film 208 is in advance formed on the gate electrodes 204.
In the thus fabricated semiconductor device if the contact hole 210 is extended over the gate electrode 204 by disalignment (FIG. 50A), the gate electrodes 204 are completely covered with the sidewall insulation film 212 and the etching stopper film 214, whereby short-circuit between a metallization layer (not shown) formed in the contact hole 210 and the gate electrodes 204 can be prevented.
As means for forming a contact hole, the so-called SAC (self-aligned contact) technique for opening a contact hole in self-alignment with a gate electrode is known.
The third conventional method using the SAC technique will be explained.
First, a device isolation film 222 is formed on a silicon substrate 220. The device isolation film 222 is formed in, e.g., the staggered arrangement as exemplified in FIG. 52A.
Then, a gate insulation film 224 is formed on the surface of the silicon substrate 220 by thermal oxidation.
Subsequently, a polycrystalline silicon film to be a gate electrode, and a silicon nitride film to be an etching stopper film are deposited on the entire surface by, e.g., CVD method, and these films are processed in a pattern of the gate electrode. The gate electrode 226 with the upper surface covered with the etching stopper film 228 is thus formed (FIG. 51A).
Then, a silicon nitride film is deposited by, e.g., CVD method, and anisotropic etching in which the etching vertically advances is performed to form a sidewall insulation film 230 on the side walls of the gate electrode 228 and the of the etching stopper film 228 (FIG. 51B).
Next, a silicon oxide film is deposited by, e.g., CVD method, and then the surface of the silicon oxide film is planarized by, e.g., CMP (Chemical Mechanical Polishing) method to form an inter-layer insulation film 232 of the silicon oxide film (FIG. 51C).
Subsequently, a photoresist 234 having an opening having an opening on a device region defined by the device isolation film 222 as shown in FIG. 52B is formed, and the inter-layer insulation film 232 is etched with the photoresist 234 as a mask (FIG. 50D).
For this etching, etching conditions which make an etching rate of the silicon nitride film forming the etching stopper film 228 and the sidewall insulation film 230 sufficiently lower than an etching rate of the silicon oxide film forming the inter-layer insulation film 232 are selected, whereby the etching stopper film 228 and the sidewall insulation film 230 in the photoresist 234 are not etched with the inter-layer insulation film 232 alone etched. That is, the contact hole 236 can be opened in self-alignment with the gate electrode 224.
However, in the above-described first conventional method, as described above, the gate electrode 204 is often exposed in the contact hole 210 due to disalignment of the lithography.
In the first and the second conventional methods, the contact hole often has size fluctuations due to disalignment in the lithography step.
That is, without the disalignment, the ends of the contact hole is defined by the sidewall insulation film 212 formed on the side walls of the inter-layer insulation film 208 as shown in FIGS. 47C and 49C. When the disalignment takes place, however, as shown in FIGS. 48B and 50B, one end of the contact hole is defined by the sidewall insulation film 212 formed on the side walls of the inter-layer insulation film 208, and the other end of the contact hole is defined by the sidewall insulation film formed on the side walls of the gate electrode 204. Consequently, the contact hole often has a smaller size as the disalignment is larger.
In the third conventional method, the contact holes which are adjacent to each other with the gate electrode therebetween are formed in respective patterns different from each other (FIG. 52B). This is because in forming in one pattern a plurality of contact holes adjacent to each other, in a case that plugs are buried in the respective contact holes by polishing, there is a high risk that the respective plugs may be short-circuited with each other, and in isolating a conductor by lithography, there is an inconvenience that residues tend to take place on the step of the contact hole, and the etching is thus very difficult.
However, in a case that as in the third conventional method, contact holes are very adjacent to each other, it is necessary that a hole size in the photoresist formed by lithography is precise, and disalignment causes the above-described fluctuations of a contact hole size, and control of disalignments must be strict.
In the third conventional method, the sidewall insulation film is formed mainly of silicon nitride film, but there is an inconvenience that the sidewall insulation film of silicon nitride film deteriorates hot carrier immunity of a transistor than the sidewall insulation film of silicon oxide film.
It is empirically known that silicon nitride film formed on an inclined portion has a higher etching rate than that formed on a flat portion. In the third conventional method, in which the inter-layer insulation film is etched with the sidewall insulation film as a mask, an etching selectivity for the silicon nitride film of the inclined region where the upper surface of the sidewall insulation film cannot be sufficiently ensured with a result that the gate electrode is often exposed in the contact hole.